1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same. In particular, the present invention relates to a method for manufacturing a semiconductor device which is appropriate for shallow trench isolation (STI) processes used to electrically isolate a great number of elements, as well as a semiconductor device obtained in accordance with this method.
2. Description of Related Art
In general, semiconductor devices have a configuration where a great number of cells made up of unit elements (for example, several thousand to several hundred million), such as transistors and capacitors, are integrated within an area restricted in accordance with the capacity of the semiconductor device. It is necessary for these unit elements to be electrically isolated (insulated) from each other so that they operate independently.
As a method of electrical isolation, LOCOS (local oxidation of silicon) methods in which recesses are formed on a semiconductor substrate and then a field oxide film is grown, and trench isolation methods in which a semiconductor substrate is etched in the vertical direction so that trench regions are formed, and then the trench regions are embedded with an insulating film, are widely known. Here, trench regions include not only regions in a plane but also regions which spread in the direction of the depth.
From among these methods, the LOCOS methods are simple and have fewer problems caused by stress from the oxide film, because the semiconductor substrate is thermally oxidized using a nitride film as a mask. Therefore, the LOCOS methods have an advantage, such that the quality of the obtained oxide film is excellent.
However, the area occupied by the element isolation regions is large in the LOCOS methods, and therefore, there are problems in terms of miniaturization and a problem arises, such that bird's beaks are formed.
Meanwhile, the trench isolation methods are methods in which a dry etching technology, such as reactive ion etching (RIE) or plasma etching is used to form narrow and deep trench regions, which are then embedded with an insulating film. In to these methods, the trench regions formed on the semiconductor substrate are embedded with an insulating film, and therefore, no bird's beaks are formed.
In addition, the surface of the insulating film with which the trench regions are embedded is flattened, and therefore, the area occupied by the element isolation regions becomes small. Thus, the trench isolation methods have an advantage, such that active regions (regions where unit elements are formed) can be secured as much as possible. In addition, in the element isolation regions obtained according to these methods, the junction leak current can be reduced in comparison with the LOCOS methods.
A trench isolation method is shown in, for example, Japanese Unexamined Patent Publication 2002-252279.
FIG. 1 is a schematic cross sectional diagram showing the semiconductor device in this gazette, and FIGS. 2A to 2H are cross sectional diagrams schematically illustrating the steps in the manufacturing method. The method for manufacturing the semiconductor device in FIG. 1 is described below in reference to FIGS. 2A to 2H.
First, a semiconductor substrate 1 is thermally oxidized so that a pad oxidation film 2 is formed. Next, a nitride film (stopper film) 3 is deposited on the pad oxide film 2 in accordance with a chemical vapor deposition method (FIG. 2A). Next, a photosensitive film is applied over the entire surface of the semiconductor substrate 1 on which the pad oxide film 2 and the nitride film 3 are formed, and the substrate is exposed to light through a mask where a trench pattern is formed, followed by development, so that a photosensitive film pattern for forming trench regions is formed.
Next, the nitride film 3 and the pad oxide film 2 are etched and removed where not covered by the photosensitive film pattern (FIG. 2B), and after that, the semiconductor substrate 1 is etched to a certain depth where not covered by the nitride film 3 and the pad oxide film 2, so that trench regions 4 are formed in the element isolation regions (FIG. 2C). In FIG. 2C, the reference number 5 indicates an active region.
Subsequently, the photosensitive film pattern is removed and the semiconductor substrate 1 washed, and after that, the semiconductor substrate 1 is thermally oxidized using the nitride film 3 as a mask, in order to improve the element isolation properties of the trench regions 4, and thus, an oxide film is grown on the inner walls of the trench regions 4 (not shown).
Next, an insulating film 6, which is a material with which the trenches are to be embedded, is deposited over the entire surface of the semiconductor substrate 1 in accordance with a chemical vapor deposition method so that the trench regions 4 are completely embedded, and the substrate is annealed if necessary, so that the density of the insulating film 6 with which the trench regions 4 are embedded increases (FIG. 2D).
After that, the insulating film 6 is removed in accordance with chemical mechanical polishing (CMP) utilizing the difference in polishing rate between the insulating film 6 and the nitride film 3, so that the upper surface of the insulating film in trench regions 4 becomes of the same level as the top of the nitride film 3, and thus, the insulating film 6 is flattened (FIG. 2E). Furthermore, the nitride film 3 which remains in the active regions 5 is removed through wet etching or dry etching, and thus, the element isolation regions are completed (FIG. 2F).
After that, appropriate impurities are implanted in the semiconductor substrate 1 under desired conditions and the pad oxide film 2 is removed (FIG. 2G). Subsequently, the gate insulating film 7 is formed, and gate electrodes 8 are formed through a well-known photolithographic method and dry etching, so that unit elements (herein, transistors) are formed (FIG. 1 and FIG. 2H).
As described above, in trench isolation methods, the CMP method is one method for flattening the insulating film with which trench regions are embedded in order to secure the photo margin required for more integrated unit elements and minimize the length of wires.
Flattening methods include BPSG reflow, aluminum reflow, SOG reflow and etch back methods, in addition to CMP methods. However, the CMP methods have an advantage, such that flattening in a wide region and flattening at low temperature are possible, which cannot be achieved through reflow or etch back. Therefore, the CMP methods are currently effective as flattening technology for various devices.